1. Design Aims
2. Example testbench
3. Why this tool?
4. Transaction Testbench
5. Summary
6. Download software

Faced with testing a new VHDL design I looked at the programs on offer to help in this task. But when I started to write down the tests I wanted to do to test out the serial inputs and outputs of my design, I found none of these programs had the ability to define anything other than very simple patterns, and the VHDL they produced was so difficult to modify I really couldn't see that they would be a help. Not to mention they were very expensive. So I decide to write my own with the aims of:

• Complex patterns
• Low cost
• Flexible

Writing down the tests I wanted:

reminded me of a spread sheet so rather than reinvent the whole wheel I wrote an extension to Excel (97+). But do not think just because you have never used Excel this program is not for you. The program help file contains a quick page of basic Excel, to get you started and all you need for even complex designs. Plus, Excel itself has a comprehensive help if you get stuck. Using Excel gave me straight off the ability to create complex interactions between cells, plus copy, paste, fill etc. On top of this my program has added the ability to:

• Read source vhdl to get signal names
• Write a complete testbench file
• Write a test vector file
• Plot the test vectors

To see how simple it is to produce a set of test vectors lets start with a serial comparator, this is rather odd but deliberately so as it serves to show how easy it is to produce complex patterns. This device has a serial input (DATA) that takes two byte values. Line AnB decides which shift register is filled. There are 3 outputs LT (less than), EQ (equal) and GT (greater than) and a line ENABLE that holds all outputs at 0 for the times when the shift registers are being loaded. Finally the part has a RESET line to clear the shift registers. The test will use values of 0, 1, 2, 4, 8, 16, 32, 64, and 128, all told 64 tests (8x8). It could have used 0 to 255 giving 65536 tests but 64 is slightly harder to implement so shows th epower of the tool better. The test process is thus load A, load B, enable and check result, repeat. The screen shot below shows the full code with explanatory notes.

As you can see, it is fairly simple. The test vector file in this case is only 64 lines but could just as easily be 65536 lines. BitN is a function to return the Nth bit of a hex number. The rest are Excel functions. This example and the VHDL source is included in the download so you can try for yourself the process of:

• Extract Signals
• Write tests (copy and paste in this case)
• Make test bench
• Make vectors
• Compile and test VHDL

The final ability is to plot the signal of the test vectors. The workbook has a special sheet called plot. Clicking its tab to bring it into view plots the signals from the last sheet starting from the selected cell's column of that sheet. The size of plot defaults to those viewable but this can be overridden by entering a value in B2.

Plus, if you open two windows and have the plot in view then changes automatically update the plot. This, slowed down, is shown below.

Or perhaps what does this tool do for me? The name of the game is to increase your efficiency. It is possible to directly write a test bench in inline VHDL but above simple designs inline VHDL starts to become complex so you will probably add a low level routine to handle the interfacing to your design and then specify the tests and results at a higher level of extraction. This tool evolved out of just such a process. VHDL editors provide no help in writing the list of test/result. This tool does. You can specify a pattern and repeat it, and repeat the repeating. You can copy just one signal or a group by dragging with the mouse, in a code editor you would have to copy, paste, paste… then edit, edit… each line. You can break tests up into groups, test one function at a time then finally retest the lot with a final rebuild. You can do a quick plot to see your signal traces. Writing with VHDL you would have to wait until you have compiled and simulated. You also don't need to compile the VHDL at each change saving more time. Listed like this, perhaps these don't sound much, but try the program and you will see that they do make a significant improvement in your efficiency. Plus, the tool is flexible. You are not limited to just signals on your component but any variable you want, except that then you will have to edit the test bench to use it. Some idea about how this could be used are:

• Providing the answer in a design for a MAC where you had only designed the interface and wanted to test that.
• Toggling a clock N times (i.e. N is the variable) to speed up testing large counters.

The limit of the tool is up to you. It certainly assists anything above a really trivial design (i.e. a few gates). The top limit is undetermined but I could see it being useful with a simple embedded processor. Really! Let's say you have a simple processor, no cache etc. The testing is a combination of bus timing checks and the response to instructions. It is easy to see how the low level checks are done but what about the instructions? To the processor these are just numbers where as humans prefer real words (or at least mnemonics). Excel has a VLOOKUP function so we can use a spare row (like row 13/14 in the picture above) for the mnemonic and get Excel to fill in the instruction code on the signals. And if we change the instruction coding the we only need to change one table. Similarly we can get Excel to work out what the result should be. In a few columns we could generate the test vectors to get the processor to add all the numbers 0-255. Copy and edit and we could be subtracting all the numbers from 0-255. etc. Isn't that simple?

This tool is also ideal for the latest innovation in testbenches, transaction style. In fact this has already been touched on but without this buzzword. A transaction based testbench works at a higher level than the signal (RTL) level. The inputs are transactions (e.g. do_read, do_write) rather than signals (e.g. write=0, write=1) which routines in the test bench, called transactors (or TVM), convert to signals. Since this tool can handle variables as well as signals it is easy to produce transaction style test benches. There are two ways to implement them (and possibly more). Firstly, with a control word e.g. an op code. This would define the transaction, the data in and out paths would be the same. Excel's functions could be used to allow mnemonics to used with Excel looking these up to give an op-code number (or error for a typo). The second way is to have multiple data paths e.g. add_data, sub_data, and then have the routines only process when their data is not ---- (don't cares).

The process of producing a testbench is: {insert component details}->{write tests}->{make test bench and vectors}. This program automates the first and the last and makes the middle, write tests, as easy as possible by providing powerful tools to make the generation of complex patterns simple. The program reads from your source and generates a functional testbench file. This file only needs to be complied once. All the tests are in the vector file so changes can be made and checked quickly. You can view a plot of the tests in the program which also helps speed the development process. Finally, the program is flexible in that you are not constraint just to DUT signals. You can add other variables, even times, and use these in the testbench. This enables working at low signal level and also working at data level, i.e. read and check given data with the read process coded into the testbench, the new name for this is transaction based testbench with the testbench routines called a transactor or TVM. You can even do both easily in the same test vectors, allowing low level and high level testing. So download it and give it a try.

Download TestBench Tool zip. This is a demo limited to 5 signals as TestBench Tool was retail software. TestBench Tool has now been made freeware so you also need to download the license file to make it a full version. See the Readme's in each zip file for how to install and how to upgrade to full version (aka register on the menu).

• None of the software is adware or spyware.
• Email addresses will not be revealed to other parties.
• Email is aggressively spam filtered so please use the contact form to get in touch.
• If you find this programs useful then feel free to link back to this site.